Dynamic semiconductor memories have storage cells in which charges are stored in storage capacitors, which can be driven by selection transistors. For the selection transistor, modern semiconductor memories, for example DRAMs (Dynamic Random Access Memory), mostly use field-effect transistors in whose channel region a channel is formed or suppressed as a function of the voltages applied to the source, gate and drain electrodes. In the case of an enhancement-type transistor, the application of a wordline voltage higher than the threshold voltage of the transistor leads to the formation of a channel, and therefore to a conductive connection between the drain electrode and the source electrode, so that information stored in the storage capacitor can be read or information can be written to the storage capacitor. In the off state, the selection transistor prevents the information stored in the storage capacitor from flowing away through the bitline. During the time when the stored information is not being interrogated, it should be kept unchanged as far as possible.
In dynamic semiconductor memories, however, the quantities of charge stored in the storage capacitors become depleted after only a short time. Leakage currents are responsible for this. Dynamic semiconductor memories are therefore refreshed at short time intervals (“refresh time”). For example, the charge of each storage capacitor of the semiconductor memory is replenished at an interval of 64 milliseconds. That is to say, it is first read in an only slightly discharged state and then rewritten more strongly. Owing to this overwriting of the quantity of charge of all the storage capacitors periodically over time, the stored quantity of charge at any time is always greater than the minimum charge that is necessary in order to unequivocally determine whether the residual charge still stored represents a digital “1” or a digital “0”.
When the transistor is off (in the case of an enhancement-type transistor, when the transistor channel is not formed) leakage currents nevertheless flow and discharge the storage capacitor, which is actually to be blocked. In the subliminal current range, the transistor is in a state of weak inversion and a small residual current flows between the source electrode and the drain electrode. This current decreases exponentially as the gate potential becomes more different from the threshold voltage, for which reason negative wordline potentials in the off state are applied in the case of n-channel transistors in modern semiconductor memories, in order to reduce this leakage current. Another leakage-current mechanism is direct interband tunnelling in the vicinity of the space-charge zones between the drain electrode on the capacitor side and the semiconductor substrate. This effect is also affected by the wordline potential (“GIDL effect”; Gate Induced Drain Leakage).
The negative wordline voltage applied in the case n-channel transistors is intended to prevent the occurrence of significant leakage currents. The dimensions and geometries of microelectronic structures are furthermore optimized via the production technology with a view to minimal leakage currents, but on the other hand it is necessary to ensure sufficiently fast charging and discharging of the storage capacitor via the transistor when it is open.